Flip chip, also known as controlled collapse chip connection (C4), is a method for interconnecting semiconductor devices, such as integrated circuit (IC) chips and microelectromechanical systems (MEMS), to chip carriers and external circuitry with join structures, such as C4 bumps (solder bumps), that have been deposited onto chip pads. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to chip carriers and external circuitry (e.g., a circuit board or another chip or wafer), the chip is flipped over so that a top side of the chip faces down, and is then aligned so that the pads align with matching pads on the chip carriers or external circuitry. Thereafter, the solder is flowed to complete the C4 interconnect.
Height values of the C4 interconnect (e.g., thicknesses of the gap between the integrated circuit chip and the chip carriers or external circuitry) are helpful data during integrated circuit chip packaging processes development and qualification. In instances where the integrated circuit chip is connected to the chip carriers or external circuitry via C4 bumps, height values of the C4 bumps are at least one component that is determinative of the height values of the interconnect between the integrated circuit chip and the chip carriers or external circuitry. Consequently, the height values of the C4 bumps and uniformity/variability of the C4 bumps provide information to evaluate cleanability under the integrate circuit chip, underfill flowability, chip join yields, and also may give insight of the shapes of the C4 bumps (e.g., dumbbell shape or oval shape) affecting reliability of the C4.
Conventionally, in order to obtain information on the height values of the C4 bumps, one or more cross-sections are taken of the C4 interconnect between the integrated circuit chip and the chip carriers or external circuitry. This method provides a height value of the C4 interconnect at the location of the cross-section, the shape of the C4 bumps at the location of the cross-section, and a few additional visual details at the location of the cross-section. However, each cross section can take hours of work to obtain, and the sample size is limited, e.g., each cross section only provides a snap shot of one location between the integrated circuit chip and the chip carriers or external circuitry. Additionally, the process is destructive to the measured interconnect device, and thus the measured interconnect device cannot be used downstream to evaluate the impact of the height of the C4 interconnect on downstream operations.